1. Technical Field
The present invention relates generally to Digital-to-Analog circuitry and, more specifically, to a method and apparatus for reducing the number of input differential pairs for a Digital-to-Analog Converter voltage interpolation amplifier.
2. Introduction
Digital-to-Analog Converter (DAC) architecture is commonly used in mixed-mode systems requiring monotonicity, wherein the DAC acts as an interface to convert a digital code to an analog signal. Conventional DAC designs typically include a differential resistor string embodiment producing output voltages. These designs attempt to extend the resolution of differential resistor string DACs by feeding the output voltages into a voltage interpolation amplifier.
One such resistor string DAC design includes an M-bit DAC combined with an N-bit voltage interpolation amplifier to achieve M+N bit total resolution, wherein the DAC is used to generate two DAC voltages with a voltage difference of 2N*VLSB, the voltage difference across a given resistor in a string of resistors in the coarse DAC circuit. The two DAC voltages are fed into the voltage interpolation amplifier and interpolated to generate the final DAC voltage output. Conventional voltage interpolation amplifier designs use 2N unary-weighted identical input differential pairs with their drains summed together and respective gates controlled by a digital code. Accordingly, as the interpolation bit, N, increases, the number of differential pairs increases exponentially for these conventional amplifiers. Each differential pair requires an independent current source; therefore, the increase in differential pairs not only requires more circuit real estate, but also results in a substantial increase in power consumption. Therefore, there is a need for an improved voltage interpolation amplifier design that reduces the circuit complexity and power consumption of current voltage interpolation designs, thereby creating a more area- and power-efficient voltage interpolation amplifier.